1. Field of the Invention
The present invention relates to a liquid crystal display control apparatus and a liquid crystal display apparatus and more particularly, to a liquid crystal display control apparatus of a passive matrix type and a liquid crystal display apparatus.
2. Description of the Related Art
In a liquid crystal display apparatus of a so-called passive matrix display type as a super-twisted nematic (STN) type wherein pixels are positioned at intersections between scan and data electrodes perpendicular to each other so that the light transmission factor of the pixel varies with a mean square of a difference between voltages applied to the scan and data electrodes; a drive frame frequency for obtaining the optimum contrast varies with the response time of liquid crystal material.
It is generally believed that the optimum contrast can be obtained when the response time of liquid crystal material (corresponding to an addition of a rise time until display on and a fall time until display off) is 300 ms and a drive frame frequency is between 90 and 120 Hz.
It is also believed that the optimum contrast can be obtained when the response time is 150 ms and the drive frame frequency is 150 Hz or when the response time is 100 ms and the drive frame frequency is 180 Hz or more.
These drive frame frequencies are higher than the drive frame frequencies of 60 to 75 Hz of a cathode-ray tube (CRT) display or thin film transistor (TFT) liquid crystal display.
Accordingly, in order to convert a display signal for the CRT display or TFT liquid crystal display to a display signal for an STN liquid crystal display, it is required to use a frame memory for saving of display data to convert it to a drive frame frequency.
In liquid crystal displays, predominant ones of driving methods for applying binary information (one bit data) of display on and off to the respective pixels of the liquid crystal display.
In order to provide a gray-scale for the liquid crystal display, special processing becomes necessary. As one of systems for implementing this special processing, there is a frame rate control (FRC) system which provides a gray-scale display by setting several frame periods as a unit period and setting the display on/off rate of each pixel in the unit period in terms of unit periods of frame periods.
FIG. 30 is a diagram for explaining an example of gray-scale processing of the FRC system.
In the example shown in FIG. 30, 4 frame periods are set as a unit period, and a pattern of display on and off (referred to as the FRC pattern, hereinafter) is switched on every unit period basis with respect to each certain size of matrix on the display screen.
In a liquid crystal display apparatus of an STN type, a means for implementing the drive frame frequency converting operation and the gray-scale processing operation of the FRC system is generally called liquid crystal controller.
FIGS. 31 and 32 schematically show block diagrams of liquid crystal controllers.
The liquid crystal controller shown in FIG. 31 is of such a type that executes the gray-scale processing operation prior to the drive frame frequency converting operation.
First, for each of colors of red (R), green (G) and blue (B), an input interface 311 accepts gray-scale data (usually, 6-to-8 bit data) of n bits per pixel.
A gray-scale processor 312 then executes the gray-scale processing operation of the FRC system according to the gray-scale data received from the input interface 311 to generate of one bit of indicate on/off data, and writes it into a frame memory 313.
Thereafter, the indicate on/off data are read out from the frame memory 313 in synchronism with the drive frame frequency of the liquid crystal output display data to be converted to a frame frequency, and then output to an STN liquid crystal display (not shown) through a liquid crystal output interface 314.
The liquid crystal controller shown in FIG. 32, on the other hand, is such a type that executes the frame frequency converting operation prior to the gray-scale processing operation.
First, for each of the colors R, G and B, an input interface 311 accepts gray-scale data (usually, 6-to-8 bit data) of n bits per pixel. After that, the gray-scale data are written into a frame memory 313.
Next, the gray-scale data are read out from the frame memory 313 in synchronism with the drive frame frequency of the liquid crystal output display data to be converted to a frame frequency, and thereafter a gray-scale processor 312 executes the gray-scale processing operation of the read gray-scale data to generate one bit of indicate on/off data.
And the gray-scale processor 312 outputs the indicate on/off data to an STN liquid crystal display (not shown) through a liquid crystal output interface 314.
Disclosed in Japanese Laid-Open Publication No. 8-87247 is a technique for displaying a video signal not conforming to a liquid crystal display of the passive matrix type.
It is therefore a first object of the present invention to provide a liquid crystal display control apparatus and liquid crystal display apparatus which can suppress moving and flickering of a gray-scale display portion and also can avoid increase in the number of pins when the apparatus is made in the form of a large scale integrated (LSI) circuit.
A second object of the present invention is to provide a liquid crystal display control apparatus and liquid crystal display apparatus which can prevent interference fringes generated when gray-scale display is carried out over upper and lower screens of an STN liquid crystal display of a so-called dual scan type.
A third object of the present invention is to provide a liquid crystal display control apparatus and liquid crystal display apparatus which, when digital gray-scale data generated from analog display data for a CRT display is used as an input signal, can suppress deterioration of quality of the gray-scale display due to an quantum error caused by conversion of the analog display data to the digital gray-scale data.
A fourth object of the present invention is to provide a liquid crystal display control apparatus and liquid crystal display apparatus which can display on a liquid crystal display a video signal with retrace lines removed therefrom.
In accordance with a first aspect of the present invention, there is provided a liquid crystal controller wherein, in accordance with gray-scale data of pixel units included in a video input signal, a display on/off rate at which pixels of units included in a video output signal to a liquid crystal display are indicated during a plurality of frame periods of the video output signal, is set in the pixel units of the video output signal in its one display scan period on a unit pixel basis to provide intermediate gray-scale display to the liquid crystal display, and which controller comprises:
a display on/off data generation circuit, in accordance with the gray-scale data of pixel units included in the video input signal, for generating display on/off data corresponding to M (M greater than N) frame periods of the video output signal in N frame periods of the video input signal on a unit pixel basis;
a write control circuit for writing display on/off data corresponding to M frames of the video output signal generated by the display on/off data generation circuit into a frame memory during N frame periods of the video input signal; and
a read control circuit for sequentially reading out, from the frame memory, display on/off data corresponding to M frames of the video output signal written in the frame memory in synchronism with frame period of the video output signal.
In this case, the gray-scale data refer to, e.g., display data for a liquid crystal display of a thin film transistor (TFT) type.
The above arrangement, display on/off data corresponding to M (M greater than N) frames of the video output signal are written into the frame memory during an N frame period of the video input signal, and the written display on/off data of the M frames are sequentially read out from the frame memory in synchronism with the frame period of the video output signal.
In this way, since the data written in the frame memory is not gray-scale data but display on/off data of one bit, a data bus width at the time of accessing the frame memory can be reduced. Accordingly, an increase in the number of pins involved when it is desired to make the controller in the form of an LSI can be suppressed.
Further, since the frame period of the video output signal can be set faster than the frame period of the video input signal, the flow or flickering of the intermediate gray-scale display part can be lightened.
In addition, gray-scale data is data of usually 6 to 8 bits per pixel, whereas display on/off data is data of one bit per pixel.
Therefore, the total number of bits in the data written in the frame memory with one frame period of the video input signal as a unit is:
(1) When gray-scale data is written in the frame memory, [(the number of pixels in one frame)xc3x976 to 8 bits].
(2) When display on/off data is written in the frame memory, [(the number of pixels in one frame)xc3x971 bitxc3x97M/N bits].
Accordingly, by setting M/N to be smaller than 6 to 8, the memory capacity can be saved when compared with that when gray-scale data is written in the frame memory.
In accordance with a second aspect of the present invention, there is provided a liquid crystal controller wherein, in accordance with gray-scale data of units each having a plurality of pixels and included in a video input signal, display on/off change-over patterns of pixels during a plurality of frame periods of the video output signal to be output to a liquid crystal display, are set to provide intermediate gray-scale display for the liquid crystal display, the liquid crystal display is of a dual scan type in which the liquid crystal display is divided into upper and lower display to be simultaneously driven, and which comprises:
a first setting circuit for setting a display on/off change-over pattern of pixels during a plurality of frame periods of the video output signal according to gray-scale data of the pixel units located in the upper display and included in the video input signal; and
a second setting circuit for setting a display on/off change-over pattern of pixels during a plurality of frame periods of the video output signal according to gray-scale data of the pixel units located in the upper display and included in the video input signal;
and wherein the second setting circuit sets the display on/off change-over data in such a manner that the display on/off change-over pattern of pixels located in the lower display is delayed by one frame of the video output signal with respect to the display on/off change-over pattern of pixels located in the upper display.
In the second aspect of the present invention having the above arrangement, the display on/off pattern of the lower display can be output as delayed by one frame with respect to that of the upper display.
In this way, since the display on/off data of pixels in the vicinity of a boundary between the upper and lower displays can be set to be included in the same frame, it can be prevented that interference fringes look like moving in the vicinity of the boundary between the upper and lower displays.
In accordance with a third aspect of the present invention, there is provided a liquid crystal controller wherein, in accordance with gray-scale data of pixel units generated by quantizing an analog gray-scale signal, display on/off change-over patterns of pixels during a plurality of frame periods of a video output signal to be output to a liquid crystal display are set to provide intermediate gray-scale display for the liquid crystal display, and the display on/off change-over patterns are previously set so that gray-scale data of pixels having adjacent values have a nearly common frame to be mutually turned on or off.
In this case, analog gray-scale signal refers to, e.g., display data for a cathode ray tube (CRT) type of display.
In the third aspect of the present invention having the above arrangement, with respect to display on/off data corresponding to one frame of the video output signal, change-over of display on/off of pixels caused by changes in the values of the gray-scale data can be smoothly made without providing an extreme change in the positional relationship between the pixel turned on and the pixel turned off.
Thus, when digital gray-scale data generated from such an analog gray-scale signal as analog display data for a CRT display are used as a video input signal, a quantization error generated a the time of converting the analog gray-scale signal to the digital gray-scale data enables suppression of image quality deterioration of intermediate gray-scale display.
In accordance with a fourth aspect of the present invention, there is provided a liquid crystal controller which comprises a vertical synchronous signal control circuit for converting a vertical synchronous signal inputted to the controller into a vertical synchronous signal having a frequency corresponding to Y (Y being a real number of 2 or more) times the frequency of the input vertical synchronous signal and supplying the converted vertical synchronous signal commonly to two scan driving circuits, and a data drive control circuit for reading out, from the frame memory, data of the video input signal stored in the memory at such a speed as readable by one frame during one period of the converted vertical synchronous signal with respect to each of 2 liquid crystal displays and supplying it to the associated data drive circuit.
Thereby a video signal corresponding to the video input signal but its retrace periods removed can be displayed on the liquid crystal displays.